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functional block diagram upo/bpo encode otr sha out ain1 s/h 2.5v ref ref out ref in latches correction logic 8-bit ladder matrix AD1671 3 3-bit flash ref com ain2 5k 5k v cc acom v ee v logic dcom 3-bit flash dac fine 4-bit flash coarse 4-bit flash 4 dac 3 12 msb dav bit 1 ?2 4 8 x4 range select rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 12-bit 1.25 msps monolithic a/d converter AD1671 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features conversion time: 800 ns 1.25 mhz throughput rate complete: on-chip sample-and-hold amplifier and voltage reference low power dissipation: 570 mw no missing codes guaranteed signal-to-noise plus distortion ratio f in = 100 khz: 70 db pin configurable input voltage ranges twos complement or offset binary output data 28-pin dip and 28-pin surface mount package out of range indicator product description the AD1671 is a monolithic 12-bit, 1.25 msps analog-to- digi tal converter with an on-board, high performance sample- and-hold amplifier (sha) and voltage reference. the AD1671 guarantees no missing codes over the full operating tempera- ture range. the combination of a merged high speed bipolar/ cmos process and a novel architecture results in a combi- nation of speed and power consumption far superior to pre- viously available hybrid implementations. additionally, the greater reliability of monolithic construction offers improved system reliability and lower costs than hybrid designs. the fast settling input sha is equally suited for both multi- plexed systems that switch negative to positive full-scale voltage levels in successive channels and sampling inputs at frequencies up to and beyond the nyquist rate. the AD1671 provides both reference output and reference input pins, al- lowing the on-board reference to serve as a system reference. an external reference can also be chosen to suit the dc accu- racy and temperature drift requirements of the application. the AD1671 uses a subranging flash conversion technique, with digital error correction for possible errors introduced in the first part of the conversion cycle. an on-chip timing gen- erator provides strobe pulses for each of the four internal flash cycles. a single encode pulse is used to control the converter. the digital output data is presented in twos complement or offset binary output format. an out-of-range signal indicates an overflow condition. it can be used with the most significant bit to determine low or high overflow. the performance of the AD1671 is made possible by using high speed, low noise bipolar circuitry in the linear sections and low power cmos for the logic sections. analog devices abcmos-1 process provides both high speed bipolar and 2-micron cmos devices on a single chip. laser trimmed thin-film resistors are used to provide accuracy and temperature stability. the AD1671 is available in two performance grades and three temperature ranges. the AD1671j and k grades are available over the 0 c to +70 c temperature range. the AD1671a grade is available over the C40 c to +85 c temperature range. the AD1671s grade is available over the C55 c to +125 c tempera- ture range. product highlights the AD1671 offers a complete single chip sampling 12-bit, 1.25 msps analog-to-digital conversion function in a 28-pin package. the AD1671 at 570 mw consumes a fraction of the power of currently available hybrids. an out of range output bit indicates when the input sig- nal is beyond the AD1671s input range. input signal ranges are 0 v to +5 v unipolar or 5 v bipolar, selected by pin strapping, with an input resistance of 10 k w . the input signal range can also be pin strapped for 0 v to +2.5 v unipolar or 2.5 v bipolar with an input resistance of 10 m w . output data is available in unipolar, bipolar offset or bipolar twos complement binary format.
dc specifications AD1671j/a/s AD1671k parameter min typ max min typ max units resolution 12 12 bits conversion time 800 800 ns accuracy integral nonlinearity (inl) 1.5 2.5 0.7 2.5 lsb (s grade) 3.0 differential nonlinearity (dnl) 11 12 bits no missing codes 11 bits guaranteed 12 bits guaranteed unipolar offsets 1 (+25 c) 9 9 lsb bipolar zero 1 (+25 c) 10 10 lsb gain error 1, 2 (+25 c) 0.1 0.35 0.1 0.35 % fsr temperature coefficients 3 unipolar offset 25 25 ppm/ c (s grade) 25 bipolar zero 25 25 ppm/ c (s grade) 30 gain error 3 30 30 ppm/ c (s grade) 40 gain error 4 20 20 ppm/ c power supply rejection 5 v cc (+5 v 0.25 v) 4 4 lsb (s grade) 5 v logic (+5 v 0.25 v) 4 4 lsb (s grade) 5 v ee (C5 v 0.25 v) 4 4 lsb (s grade) 5 analog input input ranges bipolar C2.5 +2.5 C2.5 +2.5 volts C5.0 +5.0 C5.0 +5.0 volts unipolar 0 +2.5 0 +2.5 volts 0 +5.0 0 +5.0 volts input resistance (0 v to +2.5 v or 2.5 v range) 10 10 m w (0 v to +5.0 v or 5 v range) 8 10 12 8 10 12 k w input capacitance 10 10 pf aperture delay 15 15 ns aperture jitter 20 20 ps internal voltage reference output voltage 2.475 2.5 2.525 2.475 2.5 2.525 volts output current unipolar mode +2.5 +2.5 ma bipolar mode +1.0 +1.0 ma logic inputs high level input voltage, v ih 2.0 2.0 volts low level input voltage, v il 0.8 0.8 volts high level input current, i ih (v in = v logic ) C10 +10 C10 +10 m a low level input current , i ll (v in = 0 v) C10 +10 C10 +10 m a input capacitance , c in 55pf logic outputs high level output voltage, v oh (i oh = 0.5 ma) 2.4 2.4 volts low level output voltage, v ol (i ol = 1.6 ma) 0.4 0.4 volts power supplies operating voltages v cc +4.75 +5.25 +4.75 +5.25 volts v logic +4.5 +5.5 +4.5 +5.5 volts v ee C4.75 C5.25 C4.75 C5.25 volts operating current i cc 55 68 55 68 ma i logic 6 35 35ma i ee C55 C68 C55 C68 ma power consumption 570 750 570 750 mw temperature range (specified) j/k 0 +70 0 +70 c a C40 +85 C40 +85 c s C55 +125 C55 +125 c notes 1 adjustable to zero with external potentiometers. 2 includes internal voltage reference error. 3 +25 c to t min and +25 c to t max 4 excludes internal reference drift. 5 change in gain error as a function of the dc supply voltage. 6 tested under static conditions. see figure 15 for typical curve of i logic vs. load capacitance at maximum t c . specifications subject to change without notice . (t min to t max with v cc = +5 v 6 5%, v logic = +5 v 6 10%, v ee = C5 v 6 5%, unless otherwise noted) AD1671Cspecifications rev. b C2C
AD1671 (t min to t max with v cc = +5 v 6 5%, v logic = +5 v 6 10%, v ee = C5 v 6 5%, f sample = 1 msps, f lnput = 1oo khz, unless otherwise noted) 1 ac specifications AD1671j/a/s AD1671k parameter min typ max min typ max units signal-to-noise plus distortion ratio (s/n + d) C0.5 db input 68 70 68 71 db C20 db input 50 51 db effective number of bits (enob) 11.2 11.2 bits total harmonic distortion (thd) C80 C75 C83 C75 db peak spurious or peak harmonic component C80 C77 C81 C77 db small signal bandwidth 12 12 mhz full power bandwidth 2 2 mhz intermodulation distortion (imd) 2 2nd order products C80 C75 C80 C75 db 3rd order products C85 C75 C85 C75 db notes 1 f in amplitude = C0.5 db (9.44 v p-p) bipolar mode full scale unless otherwise indicated. all measurements referred to a 0 db ( 5 v) input signal, unless otherwise indicated. 2 f a = 99 khz, f b = 100 khz with f sample = 1 msps. specifications subject to change without notice. switching specifications parameters symbol min typ max units conversion time t c 800 ns sample rate f s 1.25 msps encode pulse width high (figure 1a) t enc 20 50 ns encode pulse width low (figure 1b) t encl 20 ns dav pulse width t dav 150 300 ns encode falling edge delay t f 0ns start new conversion delay t r 0ns data and otr delay from dav falling edge t dd 1 20 75 ns data and otr valid before dav rising edge t ss 2 20 75 ns notes 1 t dd is measured from when the falling edge of dav crosses 0.8 v to when the output crosses 0.4 v or 2.4 v with a 25 pf load capacitor on each output pin. 2 t ss is measured from when the outputs cross 0.4 v or 2.4 v to when the rising edge of dav crosses 2.4 v with a 25 pf load capacitor on each output pin. specifications subject to change without notice. (for all grades t min to t max with v cc = +5 v 6 5%, v lo61c = +5 v 6 10%, v ee = C5 v 6 5%; v il = 0.8 v, v ih = 2.0 v, v ol = 0.4 v and v oh = 2.4 v) encode dav data 0 (previous) data 1 c t dav t dd t ss t t f t r t encl bit 1?2 msb, otr figure 1b. encode pulse low encode dav data 0 (previous) data 1 enc t c t dav t dd t ss t r t bit 1?2 msb, otr figure 1a. encode pulse high rev. b C3C
AD1671 rev. b C4C pin description symbol pin no. type name and function acom 27 p analog ground. ain 22, 23 ai analog inputs, ain1 and ain2. the AD1671 can be pin strapped for four input ranges: range pin strap signal input 0 to +2.5 v, 2.5 v connect ain1 to ain2 ain1 or ain2 0 to +5 v, 5 v connect ain1 or ain2 to acom ain1 or ain2 bit 1 (msb) 13 do most significant bit. bit 2Cbit 11 12-3 do data bits 2 through 11. bit 12 (lsb) 2 do least significant bit. bpo/upo 26 ai bipolar or unipolar configuration pin. see section on input range connections for details. dav 16 do data available output. the rising edge of dav indicates an end of conversion and can be used to latch current data into an external register. the falling edge of dav can be used to latch previous dam into an external register. dcom 19 p digital ground. encode 17 di the analog input is sampled on the rising edge of encode. msb 14 do inverted most significant bit. provides twos complement output data format. otr 15 do out of range is active high when the analog input is out of range. see output data format, table iii. ref com 20 ai ref com is the internal reference ground pin. ref com should be connected as indicated in the grounding and decoupling rules and optional external reference connection sections. ref in 24 ai ref in is the external 2.5 v reference input. ref out 21 ao ref out is the internal 2.5 v reference output. sha out 25 ao no c onnect for bipolar input ranges. connect sha out to bpo/upo for unipolar i nput ranges. v cc 28 p +5 v analog power. v ee 1 p C5 v analog power. v logic 18 p +5 v digital power. type: ai = analog input; ao = analog output; di = digital input; do = digital outputs; p = power. pin configuration acom bpo/upo dcom encode dav otr msb bit 12 (lsb) bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (msb) ain1 ref com ref out ain2 sha out 1 2 3 7 28 27 26 22 8 9 10 21 20 19 11 12 18 17 4 5 25 24 6 23 top view (not to scale) 13 14 16 15 AD1671 v ee v cc v logic ref in
AD1671 rev. b C5C absolute maximum ratings* parameter with respect to min max units v cc acom C0 5 +6.5 volts v ee acom C6.5 +0.5 volts v logic dcom C0.5 +6.5 volts acom dcom C1.0 +1.0 volts v cc v logic C6.5 +6.5 volts encode dcom C0.5 v logic + 0.5 volts ref in acom C0.5 v cc + 0.5 volts ain acom C11.0 +11.0 volts bpo/upo acom C0.5 v cc + 0.5 volts junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1671 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package model 1 linearity range option 2, 3 AD1671jq 2.5 lsb 0 c to +70 c q-28 AD1671kq 2 lsb 0 c to +70 c q-28 AD1671jp 2.5 lsb 0 c to +70 c p-28a AD1671kp 2 lsb 0 c to +70 c p-28a AD1671aq 2.5 lsb C40 c to +85 c q-28 AD1671ap 2.5 lsb C40 c to +85 c p-28a AD1671sq 3 lsb C55 c to +125 c q-28 notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to analog devices military products databook or current AD1671/883 data sheet. 2 p = plastic leaded chip carrier, q = cerdip. 3 analog devices reserves the right to ship side brazed ceramic packages in lieu of cerdip.
AD1671 rev. b C6C definitions of specifications integral nonlinearity (inl) integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb (1.22 mv for a 10 v span) before the first code transition (all zeros to only the lsb on). full-scale is defined as a level 1 1/2 lsb beyond the last code transition (to all ones). the deviation is measured from the low side transition of each particular code to the true straight line. differential linearity error (no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from the ideal value. thus every code has a finite width. guaranteed no missing codes to 11- or 12-bit res olution indicates that all 2048 and 4096 codes, respec- tively, must be present over all operating ranges. no missing codes to 11 bits (in the case of a 12-bit resolution adc) also means that no two consecutive codes are missing. unipolar offset the first transition should occur at a level 1/2 lsb above analog common. unipolar offset is defined as the deviation of the ac- tual from that point. this offset can be adjusted as discussed later. the unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments. bipolar zero in the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 lsb be- low analog common. the bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. gain error the last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 lsb below the nominal full scale (4.9963 volts for 5.000 volts full scale). the gain error is the deviation of the actual level at the last transition from the ideal level. the gain error can be adjusted to zero as shown in figures 4 through 7. temperature coefficients the temperature coefficients for unipolar offset, bipolar zero and gain error specify the maximum change from the initial (+25 c) value to the value at t min or t max . power supply rejection one of the effects of power supply error on the performance of the device will be a small change in gain. the specifications show the maximum full-scale change from the initial value with the supplies at the various limits. dynamic specifications signal-to-noise plus distortion (s/ n+d) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components, including har- monics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) enob is calculated from the expression (s/n+d) = 6.02n + 1.76 db, where n is equal to the effective number of bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is ex- pressed as a percentage or in decibels. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products of order (m + n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. . . . intermodulation terms are those for which m or n is not equal to zero. for example, the second order terms are (fa + fb) and (fa C fb), and the third or- der terms are (2 fa + fb), (2 fa C fb), (fa + 2 fb) and (2fb C fa). the imd products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distor- tion terms. the two signals are of equal amplitude and the peak value of their sum is C0.5 db from full scale. the imd products are normalized to a 0 db input signal. peak spurious or peak harmonic component the peak spurious or peak harmonic component is the largest spectral component, excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full- scale input signal. aperture delay aperture delay is the difference between thc switch delay and the analog delay of the sha. this delay represents the point in time, relative to the rising edge of encode input, that the analog input is sampled. aperture jitter aperture jitter is the variation in aperture delay for successive samples. full power bandwidth the input frequency at which the amplitude of the recon- structed fundamental is reduced by 3 db for a full-scale input.
AD1671 rev. b C7C theory of operation the AD1671 uses a successive subranging architecture. the analog-to-digital conversion takes place in four independent steps or flashes. the sampled analog input signal is subranged to an intermediate residue voltage for the final 12-bit result by utilizing multiple flashes with subtraction dacs (see the AD1671 functional block diagram). the AD1671 can be configured to operate with unipolar (0 v to +5 v, 0 v to +2.5 v) or bipolar ( 5 v, 2.5 v) inputs by con- necting ain (pins 22, 23), sha out (pin 25) and bpo/upo (pin 26) as shown in figure 2. ?.5v to +2.5v ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out sha ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out 0 to +2.5v sha a. 0 v to +2.5v input range b. 2.5 v input range ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out 5v sha ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out 0 to +5v sha c. 0 v to +5 v input range d. 5 v input range figure 2. AD1671 input range connections the AD1671 conversion cycle begins by simply providing an active high level on the encode pin (pin 17). the rising edge of the encode pulse starts the conversion. the falling edge of the encode pulse is specified to operate within a win- dow of time, less than 50 ns after the rising edge of encode or after the falling edge of dav. the time window prevents digitally coupled noise from being introduced during the final stages of conversion. an internal timing generator circuit accu- rately controls sha, flash and dac timing. upon receipt of an encode command the input voltage is held by the front-end sha and the first 3-bit flash converts the analog input voltage. the 3-bit result is passed to a correction logic register and a segmented current output dac. the dac output is connected through a resistor (within the range/span select block) to sha out. a residue voltage is created by sub- tracting the dac output from sha out, which is less than one eighth of the full-scale analog input. the second flash has an input range that is configured with one bit of overlap with the previous dac. the overlap allows for errors during the flash conversion. the first residue voltage is connected to the second 3-bit flash and to the noninverting input of a high speed, differ- ential, gain of eight amplifier. the second flash result is passed to the correction logic register and to the second segmented cur- rent output dac. the output of the second dac is connected to the inverting input of the differential amplifier. the differen- tial amplifier output is connected to a two-step, backend, 8-bit flash. this 8-bit flash consists of coarse and fine flash convert- ers. the result of the coarse 4-bit flash converter, also config- ured to overlap one bit of dac 2, is connected to the correction logic register and selects one of 16 resistors from which the fine 4-bit flash will establish its span voltage. the fine 4-bit flash is connected directly to the output latches. the internal timing generator automatically places the sha into the acquire mode when dav goes low. upon completion of conversion (when dav is set high), the sha has acquired the analog input to the specified level of accuracy and will remain in the sample mode until the next encode command. the AD1671 will flag an out-of-range condition when the input voltage exceeds the analog input range. otr (pin 15) is active high when an out-of-range high or low condition exists. bits 1C12 are high when the analog input voltage is greater than the selected input range and low when the analog input is less than the selected input range. AD1671 dynamic performance the AD1671 is specified for dc and dynamic performance. a sampling converters dynamic performance reflects both quan- tizer and sample-and-hold amplifier (sha) performance. quan- tizer nonlinearities, such as inl and dnl, can degrade dynamic performance. however, a sha is the critical element which has to accurately sample fast slewing analog input signals. the AD1671s high performance, low n oise, patented on-chip sha minimizes distortion and noise specifications. nonlinearities are minimized by using a fast slewing, low noise architecture and subregulation of the sampling switch to provide constant offsets (therefore reducing input signal dependent nonlinearities). figure 3 is a typical 2k point fast fourier transform (fft) plot of a 100 khz input signal sampled at 1 mhz. the funda- mental amplitude is set at C0.5 db to avoid input signal clipping of offset or gain errors. note the total harmonic distortion is ap- proximately C81 db, signal to noise plus distortion is 71 db and the spurious free dynamic range is 84 db. signal amplitude ?db 0 ?00 ?0 ?5 ?5 frequency 0 figure 3. AD1671 fft plot, f in = 100 khz, f sample = 1 mhz
AD1671 rev. b C8C 85 40 0 50 45 ?5 ?0 55 60 65 70 75 80 ? ?0 ?5 ?0 ?5 ?0 ?5 ?0 analog input ?db spurious free dynamic range ?db figure 7. spurious free dynamic range vs. input amplitude, f in = 250 khz applying the AD1671 grounding and decoupling rules proper grounding and decoupling should be a primary design objective in any high speed, high resolution system. the AD1671 separates analog and digital grounds to optimize the management of analog and digital ground currents in a system. the AD1671 is designed to minimize the current flowing from ref com (pin 20) by directing the majority of the current from v cc (+5 vCpin 28) to v ee (C5 vCpin 1). minimizing ana- log ground currents hence reduces the potential for large ground voltage drops. this can be especially true in systems that do not utilize ground planes or wide ground runs. ref com is also configured to be code independent, therefore reducing input de- pendent analog ground voltage drops and errors. code depen- dent ground current is diverted to acom (pin 27). also critical in any high speed digital design is the use of proper digital grounding techniques to avoid potential cmos ground bounce. figure 3 is provided to assist in the proper layout, grounding and decoupling techniques. ain1 ref in bpo/upo acom bit 1 bit 12 dcom AD1671 encode dav otr msb agp* dgp* +5v 5v *ground plane recommended ain2 ref out sha out ref com 1 m f v cc v ee v logic v ( 5v) in 1 18 28 +5v 0.1 m f 10 m f 23 22 20 27 19 25 26 24 21 13 2 17 16 15 14 0.1 m f10 m f 0.1 m f10 m f figure 8. AD1671 grounding and decoupling figure 4 plots both s/(n+d) and effective number of bits (enob) for a 100 khz input signal sampled from 666 khz to 1.25 mhz. sampling frequency ?khz 72.5 68 1250 68.5 70.5 714 666 69 69.5 70 71 71.5 72 1111 1000 909 833 769 s/(n+d) ?db 11.75 11.50 11.25 11.00 effective number of bits figure 4. s/(n/d) vs. sampling frequency, f in = 100 khz figure 5 is a thd plot for a full-scale 100 khz input signal with the sample frequency swept from 666 khz to 1.25 mhz. ?8 ?6 1250 ?4 ?6 714 666 ?2 ?0 ?8 ?4 ?2 ?0 1111 1000 909 833 769 sampling frequency ?khz thd ?db figure 5. thd vs. sampling rate, f in = 100 khz the AD1671s sfdr performance is ideal for use in communi- cation systems such as high speed modems and digital radios. the sfdr is better than 84 db with sample rates up to 1 .11 mhz and increases as the input signal amplitude is attenuated by ap- proximately 3 db. note also the sfdr is typically better than 80 db with input signals attenuated by up to C7 db. 1250 714 666 1111 1000 909 833 769 sampling frequency ?khz spurious free dynamic range ?db ?6 ?8 ?4 ?6 ?2 ?0 ?8 ?4 ?2 ?0 ?8 ?0 figure 6. spurious free dynamic range vs. sampling rate, f in = 100 khz
AD1671 rev. b C9C table i is a list of grounding and decoupling rules that should be reviewed before laying out a printed circuit board. table i. grounding and decoupling guidelines power supply decoupling comment capacitor values 0.1 m f (ceramic) and 1 m f (tantalum) surface mount chip capacitors recommended to reduce lead inductance capacitor locations directly at positive and negative supply pins to common ground plane reference (ref out) capacitor value 1 m f (tantalum) to acom grounding analog ground ground plane or wide ground return connected to the analog power supply reference ground critical common connections (ref com) should be star connected to ref com (as shown in figure 8) digital ground ground plane or wide ground return connected to the digital power supply analog and digital ground connected together once at the AD1671 unipolar (0 v to +5 v) calibration the AD1671 is factory trimmed to minimize offset, gain and linearity errors. in some applications the offset and gain errors of the AD1671 need to be externally adjusted to zero. this is accomplished by trimming the voltage at ain2 (pin 22). the circuit in figure 9 is recommended for calibrating offset and gain errors of the AD1671 when configured in the 0 v to +5 v input range. if the offset trim resistor r1 is used, it should be trimmed as follows, although a different offset can be set for a particular system requirement. this circuit will give approxi- mately 5 mv of offset trim range. nominally the AD1671 is intended to have a 1/2 lsb offset so that the exact analog input for a given code will be in the middle of that code (halfway be- tween the transitions to the codes above it and below it). thus, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 lsb (0.61 mv for 5 v range). the gain trim is done by applying a signal 1 1/2 lsbs below the nominal full scale (4.998 v for a 5 v range). trim r2 to give the last transition (1111 1111 1110 to 1111 1111 1111). this circuit will give approximately 0.5% fs of adjustment range. r2 50 w gain adj ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out sha 1? 50k +5v ?v offset adj r1 10k 25 w 0 to +5v v in figure 9. unipolar (0 v to +5 v) calibration bipolar ( 6 5 v) calibration the connections for the bipolar 5 v input range is shown in figure 10. r2 50 w gain adj ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out sha 1? 50k +5v ?v offset adj r1 10k 25 w v in ?v to +5v figure 10. bipolar ( 5 v) calibration bipolar calibration is similar to unipolar calibration. first, a sig- nal 1/2 lsb above negative full scale (C4.9988 v) is applied and r1 is trimmed to give the first transition (0000 0000 0000 to 0000 0000 0001). then a signal 1 1/2 lsb below positive full scale (+4.9963 v) is applied and r2 is trimmed to give the last transition (1111 1111 1110 to 1111 1111 1111).
AD1671 rev. b C10C unipolar (0 v to +2.5 v) calibration the connections for the 0 v to +2.5 v input range calibration is shown in figure 11. figure 11 shows an example of how the offset error can be trimmed in front of the AD1671. the proce- dure for trimming the offset and gain errors is the same as for the unipolar 5 v range. ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out sha offset adj +15v 1k 0 to +2.5v v in 10k 10k r2 2k gain adj 1? r1 ad845 1k w 390 w figure 11. unipolar (0 v to +2.5 v) calibration bipolar ( 6 2.5 v) calibration the connections for the bipolar 2.5 v input range is shown in figure 12. ain1 ain2 5k 5k sha out bpo/upo AD1671 ref in ref out sha offset adj +15v 1k v in 10k 10k r2 2k gain adj 1? r1 ad845 1k w 390 w ?.5v to +2.5v figure 12. bipolar ( 2.5 v) calibration output latches figure 13 shows the AD1671 connected to the 74hc574 octal d-type edge-triggered latches with 3-state outputs. the latch can drive highly capacitive loads (i.e., bus lines, i/o ports) while maintaining the data signal integrity. the maximum setup and hold times of the 574 type latch must be less than 20 ns (t dd and t ss minimum). to satisfy the requirements of the 574 type latch the recommended logic families are s, as, als, f or bct. new data from the AD1671 is latched on the rising edge of the dav (pin 16) output pulse. previous data can be latched by inverting the dav output with a 7404 type inverter. bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 dav data bus 3-state control AD1671 1d 2d 3d 4d 5d 6d 7d 8d clock 1q 2q 3q 4q 5q 6q 7q 8q 74hc574 oc 1d 2d 3d 4d 5d 6d 7d 8d clock 1q 2q 3q 4q 5q 6q 7q 8q 74hc574 oc figure 13. AD1671 to output latches out of range an out-of-range condition exists when the analog input voltage is beyond the input range (0 v to +2.5 v, 0 v to +5 v, 2.5 v, 5 v) of the converter otr (pin 15) is set low when the analog input v oltage is within the analog input range. otr is set high and will remain high when the analog input voltage exceeds the input range by typically 1/2 lsb (otr transition is tested to 6 lsbs of accuracy) from the center of the full-scale output codes. otr will remain high until the analog input is within the input range and another conversion is completed. by logical anding otr with the msb and its complement, overrange high or underrange low conditions can be detected. table ii is a truth table for the over/under range circuit in figure 14. sys- tems requiring programmable gain conditioning prior to the AD1671 can immediately detect an out-of-range condition, thus eliminating gain selection iterations. table ii. out-of-range truth table otr msb analog input is 0 0 in range 0 1 in range 1 0 underrange 1 1 overrange msb otr msb over = "1" under = "1" figure 14. overrange or underrange logic
AD1671 rev. b C11C table iii. output data format input analog digital range coding input l output otr 2 0 v to +2.5 v straight binary C0.0003 v 0000 0000 0000 1 0 v 0000 0000 0000 0 +2.5 v 1111 1111 1111 0 3 +2.5003 v 1111 1111 1111 1 0 v to +5 v straight binary C0.0006 v 0000 0000 0000 1 0 v 0000 0000 0000 0 +5 v 1111 1111 1111 0 3 +5.0006 v 1111 1111 1111 1 C2.5 v to +2.5 v offset binary C2.5006 v 0000 0000 0000 1 C2.5 v 0000 0000 0000 0 +2.5 v 1111 1111 1111 0 3 +2.4994 v 1111 1111 1111 1 C5 v to +5 v offset binary C5.0012 v 0000 0000 0000 1 C5 v 0000 0000 0000 0 +5 v 1111 1111 1111 0 3 +4.9988 v 1111 1111 1111 1 C2.5 v to +2.5 v twos complement C2.5006 v 1000 0000 0000 1 (using msb ) C2.5 v 1000 0000 0000 0 +2.5 v 0111 1111 1111 0 3 +2.4994 v 0111 1111 1111 1 C5 v to +5 v twos complement C5.0012 v 1000 0000 0000 1 (using msb ) C5 v 1000 0000 0000 0 +5 v 0111 1111 1111 0 3 +4.9988 v 0111 1111 1111 1 notes 1 voltages listed are with offset and gain errors adjusted to zero. 2 typical performance. output data format the AD1671 provides both msb and msb outputs, delivering data in positive true straight binary for unipolar input ranges and positive true offset binary or twos complement for bipolar input ranges. straight binary coding is used for systems that ac- cept positive-only signals. if straight binary coding is used with bipolar input signals, a 0 v input would result in a binary output of 2048. the application software would have to subtract 2048 to determine the true input voltage. host registers typically per- form math on signed integers and assume data is in that format. twos complement format minimizes software overhead which is especially important in high speed data transfers, such as a dma operation. the cpu is not bogged down performing data conversion steps, hence the total system throughput is increased. optional external reference the AD1671 includes an onboard +2.5 v reference. the refer- ence input pin (ref in) can be connected to reference output pin (ref out) or a standard external +2.5 v reference can be selected to meet specific system requirements. fast switching in- put dependent currents are modulated at the reference input. the reference input voltage can be held with the use of a capaci- tor. to prevent the AD1671s onboard reference from oscil- lating when not connected to ref in, ref out must be connected to +5 v. it is possible to connect ref out to +5 v due to its output circuit implementation which shuts down the reference. i logic vs. conversion rate figure 15 is the typical logic supply current vs. conversion rate for various capacitor loads on the digital outputs. 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1m conversion rate ?hz ma 1k 10k 100k cl = 50pf cl = 30pf cl = 0pf figure 15. i logic vs. conversion rate for various capacitive loads on the digital outputs
AD1671 rev. b C12C applications AD1671 to adsp-2100a figure 16 demonstrates the AD1671 to adsp-2100a interface. the 2100a with a clock frequency of 12.5 mhz can execute an instruction in one 80 ns cycle. the AD1671 is configured to perform continuous time sampling. the dav output of the AD1671 is asserted at the end of each conversion. dav can be used to latch the conversion result into the two 574 octal d-latches. the falling edge of the sampling clock is used to generate an interrupt (irq3) for the processor. upon interrupt, the adsp-2100a starts a data memory read by providing an address on the dma bus. the decoded address generates oe for the latches and the processor reads their output over the dma bus. the conversion result is read within a single proces- sor cycle. +5v adsp- 2100a dma0:13 dma0:15 dmack address bus q0:7 d0:7 574 oe q0:7 d0:7 574 oe data bus d0:3 dav bit1:12 encode 16 8 4 8 4 dmrd irq3 AD1671 sampling clock decode 8 figure 16. AD1671 to adsp-2100a interface AD1671 to adsp-2101/2102 figure 17 is identical to the 2100a interface except the sam- pling clock is used to generate an interrupt (irq2) for the pro- cessor. upon interrupt the adsp-2100a starts a data memory read by providing an address on the address (a) bus. the de- code address generates oe for the d-latches and the processor reads their output over the data (d) bus. reading the conver- sion result is thus completed within a single processor cycle. adsp-2101 a0:13 d0:15 address bus decode q0:7 d0:7 574 oe q0:7 d0:7 574 oe data bus d0:3 16 8 4 8 8 4 rd irq2 sampling clock dav bit1:12 encode AD1671 figure 17. AD1671 to adsp-2101/adsp-2102 interface
AD1671 rev. b C13C component list parts list type reference designator description r1, r2 resistor, 5%, 0.5 w, 100 w r3, r4, r5 resistor, 1%, 49.9 w r6 100 w trim potentiometer r7 resistor 1%, 4.99 k w optional r8 x w trim potentiometer, optional r9, r11 resistor, 1%, 4.99 k w r10 resistor, 1%, 10 k w r12 resistor, 1%, 2.49 k w r13 resistor, 1%, 787 w r14 resistor, 1%, 249 w r15Cr28 resistor, 5%, 22 w c1, c3, c5 cap, tantalum, 22 m f c2, c4, c6, c8, c10 cap, ceramic, 0.01 m f c7, c9, c15, c16 cap, tantalum, 10 m f c11, c12, c13, c14, c17 cap, ceramic, 0.1 m f c18 cap, ceramic, 1.0 m f c19Cc22 cap, ceramic, 0.1 m f c23 cap, mica, 100 pf c24 cap, ceramic, 0.001 m f u1 78l05 +5 v regulator u2 79l05 C5 v regulator u3 AD1671 u4Cu5 74hc573 drivers u6 ad568 w1Cw3 bnc jacks j1Cj15 jumpers and headers metal binding posts s1 wide 28-pin socket s2 narrow 20-pin socket s3 narrow 24-pin socket sw1Csw3 secma spdt switch tp1, tp2, tp4Ctp6 test point, red tp3, tp7, tp10, tp13 test point, black tp8, tp9, tp11, tp12, tp14 test point, white p1 40-pin connector male + hooks
AD1671 rev. b C14C figure 18. AD1671/eb pcb layoutsilkscreen layer
AD1671 rev. b C15C figure 19. AD1671/eb pcb layoutcomponent side figure 20. AD1671/eb pcb layoutsolder side
AD1671 rev. b C16C outline dimensions dimensions shown in inches and (mm). 28-lead plcc (p-28a) package 28-pin cerdip (q-28) package c1616aC10C10/93 printed in u.s.a.

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